ADC1006S055 Datasheet, PDF (11/30 Pages) NXP Semiconductors – Single 10 bits ADC, up to 55 MHz or 70 MHz

Integrated Device Technology
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
Table 6. Characteristics …continued
V_CCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; V_CCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V;
V_CCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; T_amb = 40 C to +85 C;
V_I(IN)(p-p)  V_I(INN)(p-p) = 1.9 V; V_VREF = V_CCA3  1.75 V; V_I(cm) = V_CCA3  1.6 V; typical values measured at V_CCA = V_CCD = 5 V
and V_CCO = 3.3 V, T_amb = 25 C and C_L = 10 pF; unless otherwise specified.
Symbol Parameter
Conditions
Test^[1] Min
Typ
Max
Unit
Timing (C_L = 10 pF)^[9]
t_d(s)
sampling delay time
t_h(o)
output hold time
t_d(o)
output delay time
C
-
C
4
C
-
0.25
1
ns
6.4
-
ns
9.0
13
ns
3-state output delay times; see Figure 4
t_dZH
float to active HIGH
delay time
C
-
5.1
9.0
ns
t_dZL
float to active LOW
delay time
C
-
7.0
11
ns
t_dHZ
active HIGH to float
delay time
C
-
9.7
14
ns
t_dLZ
active LOW to float
delay time
C
-
9.5
13
ns
[1] D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested.
[2] The circuit has two clock inputs: CLK and CLKN. There are 5 modes of operation:
a) PECL mode 1: (DC level vary 1 : 1 with V_CCD) CLK and CLKN inputs are at differential PECL levels.
b) PECL mode 2: (DC level vary 1 : 1 with V_CCD) CLK input is at PECL level and sampling is taken on the falling edge of the clock input
signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via a 100 nF capacitor.
c) PECL mode 3: (DC level vary 1 : 1 with V_CCD) CLKN input is at PECL level and sampling is taken on the rising edge of the clock
input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor.
d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p) and with a DC level
of 2.5 V, the sampling takes place at the falling edge of the clock signal. When driving the CLKN input with the same signal, sampling
takes place at the rising edge of the clock signal. It is recommended to decouple the CLKN or CLK input to DGND via a 100 nF
capacitor.
e) TTL mode 1: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal. In that case CLKN pin has
to be connected to the ground.
[3] The ADC input range can be adjusted with an external reference connected to VREF pin. This voltage has to be referenced to V_CCA;
see Figure 12.
[4] The 3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave.
[5] Total Harmonic Distortion (THD) is obtained with the addition of the first five harmonics:
THD = 20 log
_----_{-----2---H-----}_---²_-----+_------_---_{-----3---H-----}_---²_-----+_{-----a-}_---_{1----H-4---H----2-}_---²_-----+_------_---_-----_---²_-----+_------_---_{-----6----H-----}_--²_--
where _1H is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input; see Figure 6.
[6] Signal-to-noise ratio (S/N) takes into account all harmonics above five and noise up to Nyquist frequency; see Figure 8.
[7] Effective number of bits are obtained via a Fast Fourier Transform (FFT). The calculation takes into account all harmonics and noise up
to half of the clock frequency (Nyquist frequency). Conversion to SIgnal-to_Noise_Distortion ratio (SINAD) is given by
SINAD = ENOB  6.02 + 1.76 dB; see Figure 5.
[8] Intermodulation measured relative to either tone with analog input frequencies of 20 MHz and 20.1 MHz. The two input signals have the
same amplitude and the total amplitude of both signals provides full-scale to the converter (6 dB below full scale for each input signal).
IMD3 is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product.
[9] Output data acquisition: the output data is available after the maximum delay of t_d(o); see Figure 3.
ADC1006S055_070_3
Product data sheet
Rev. 03 — 2 July 2012
© IDT 2012. All rights reserved.
11 of 30