8T49N1012 Datasheet, PDF (11/57 Pages) Integrated Device Technology – FemtoClock NG 12-Output Frequency Synthesizer

8T49N1012 Datasheet
I²C Master Mode
When operating in I²C mode, the 8T49N1012 has the capability to
become a bus master on the I²C bus for the purposes of reading its
configuration from an external I²C EEPROM. Only a block read cycle
will be supported.
As an I²C bus master, the 8T49N1012 will support the following
functions:
• 7-bit addressing mode
• Base address register for EEPROM
• Validation of the read block via CCITT-8 CRC check against value
stored in last byte (B4h) of EEPROM
• Support for 100kHz and 400kHz operation with speed negotiation.
If bit d0 is set at Byte address 05h in the EEPROM, this will shift
from 100kHz operation to 400kHz operation.
• Support for 1- or 2-byte addressing mode
• Master arbitration with programmable number of retries
• Fixed-period cycle response timer to prevent permanently hanging
the I²C bus.
• Read will abort with an alarm (BOOTFAIL) if any of the following
conditions occur: Slave NACK, Arbitration Fail, Collision during
Address Phase, CRC failure, Slave Response time-out
The 8T49N1012 will not support the following functions:
• I²C General Call
• Slave clock stretching
• I²C Start Byte protocol
• EEPROM Chaining
• CBUS compatibility
• Responding to its own slave address when acting as a master
• Writing to external I²C devices including the external EEPROM
used for booting
Sequential Read (1‐byte offset address)
S
Dev Addr + W
A
Offset Addr
A
Sr
Dev Addr + R
A
Data 0
A
Data 1
A
A
Data n
A
P
Sequential Read (2‐byte offset address)
S
Dev Addr + W
A Offset Addr MSB A Offset Addr LSB A
Sr
Dev Addr + R
A
Data 0
A
Data 1
A
from master to slave
from slave to master
S = start
Sr = repeated start
A = acknowledge
A = none acknowledge
P = stop
Figure 4. I²C Master Read Cycle Sequencing
A
Data n
A
P
©2016 Integrated Device Technology, Inc.
11
October 28, 2016