89HPES12N3 Datasheet, PDF (11/28 Pages) Integrated Device Technology – Supports one virtual channel

IDT 89HPES12N3 Data Sheet
Parameter
Description
Min¹
Typical¹
T_{RX-EYE-MEDIUM TO}
MAX JITTER
T_{RX-IDLE-DET-DIFF-}
ENTER TIME
T_RX-SKEW
Max time between jitter median & max deviation
Unexpected Idle Enter Detect Threshold Integration Time
Lane to lane input skew
Table 9 PCIe AC Timing Characteristics (Part 2 of 2)
1. _{Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.0a}
Max¹
0.3
10
20
Units
UI
ms
ns
Signal
Symbol
Reference
Edge
Min
Max Unit
Timing
Diagram
Reference
GPIO
GPIO[7:0]¹
Tpw_13b²
None
50 — ns
Table 10 GPIO AC Timing Characteristics
1. _{GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if}
they are asynchronous.
2. _{The values for this symbol were determined by calculation, not by testing.}
Signal
Symbol
Reference
Edge
Min
Max
Unit
Timing
Diagram
Reference
JTAG
JTAG_TCK
JTAG_TMS¹,
JTAG_TDI
JTAG_TDO
JTAG_TRST_N
Tper_16a
none
50.0
—
Thigh_16a,
Tlow_16a
10.0
25.0
Tsu_16b
JTAG_TCK rising
2.4
—
Thld_16b
1.0
—
Tdo_16c
JTAG_TCK falling
—
20
Tdz_16c²
—
20
Tpw_16d²
none
25.0
—
ns
See Figure 4.
ns
ns
ns
ns
ns
ns
Table 11 JTAG AC Timing Characteristics
1. _{The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N}
changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK
when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
2. _{The values for this symbol were determined by calculation, not by testing.}
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April 9, 2010