89HPES12N3 Datasheet, PDF (1/28 Pages) Integrated Device Technology – Supports one virtual channel

12-lane 3-Port
PCI Express® Switch
®
89HPES12N3
Data Sheet
Device Overview
The 89HPES12N3 is a member of IDT’s PRECISE™ family of PCI
Express® switching solutions. The PES12N3 is a 12-lane, 3-port periph-
eral chip that performs PCI Express Base switching with a feature set
optimized for high performance applications such as servers, storage,
and communications/networking. It provides connectivity and switching
functions between a PCIe® upstream port and two downstream ports or
peer-to-peer switching between downstream ports.
Features
◆ _{High Performance PCI Express Switch}
– Three x4 ports with 12 PCI Express lanes total
– Delivers 6 GBps (48 Gbps) aggregate switching capacity
– Low latency cut-through switch architecture
– Supports 128 to 2048 byte maximum payload size
– Supports one virtual channel
– PCI Express Base specification Revision 1.0a compliant
◆ _{Flexible Architecture with Numerous Configuration Options}
– Port arbitration schemes utilizing round robin or weighted
round robin algorithms
– Supports automatic per port link with negotiation (x4, x2, or x1)
– Supports static lane reversal on all ports
– Supports polarity inversion
– Supports locked transactions, allowing use with legacy soft-
ware
– Ability to load device configuration from serial EEPROM
Block Diagram
◆ _{Highly Integrated Solution}
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates 12 2.5 Gbps embedded SerDes, 8B/10B encoder/
decoder (no separate transceivers needed)
◆ _{Reliability, Availability, and Serviceability (RAS) Features}
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports ECRC passed through
– Supports PCI Express Native Hot-Plug
• Compatible with Hot-Plug I/O expanders used on PC moth-
erboards
– Supports Hot-Swap
◆ _{Power Management}
– Supports PCI Power Management Interface specification,
Revision 1.1 (PCI-PM)
– Unused SerDes are disabled
– Supports Advanced Configuration and Power Interface Speci-
fication, Revision 2.0 (ACPI) supporting active link state
◆ _{Testability and Debug Features}
– Built in SerDes Pseudo-Random Bit Stream (PRBS) generator
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
Frame Buffer
3-Port Switch Core
Route Table
Port
Arbitration
SScchheedduulelerr
Transaction Layer
Data Link Layer
Multiplexer/Demultiplexer
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Multiplexer/Demultiplexer
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Multiplexer/Demultiplexer
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
12 PCI Express Lanes
One x4 Upstream Port and Two x4 Downstream Ports
Figure 1 Internal Block Diagram
© 2010 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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April 9, 2010
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