IDT72T51233 Datasheet, PDF (10/55 Pages) Integrated Device Technology – 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits

IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTIONS (CONTINUED)
Symbol &
Pin No.
SI
(Continued)
(L1)
Name
Serial In
I/O TYPE
Description
HSTL-LVTTL modetheserialdatainputisloadedintothefirstdeviceinachain.WhenthatdeviceisloadedanditsSENO
INPUT hasgoneLOW,thedatapresentonSIwillbedirectlyoutputtotheSOoutput.TheSOpinofthefirstdevice
connects to the SI pin of the second and so on. The multi-queue device setup registers are shift registers.
SO
Serial Out
HSTL-LVTTL This output is used in expansion mode and allows serial data to be passed through devices in the chain
(M3)
OUTPUT to complete programming of all devices. The SI of a device connects to SO of the previous device in the
chain. The SO of the final device in a chain should not be connected.
TCK⁽²⁾
(A8)
JTAG Clock
LVTTL
INPUT
Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test
operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising
edge of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used this signal
needs to be tied to GND.
TDI⁽²⁾
JTAG Test Data LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
(B9)
Input
INPUT operation,testdataseriallyloadedviatheTDIontherisingedgeofTCKtoeithertheInstructionRegister,
ID Register and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.
TDO⁽²⁾
(A9)
JTAG Test Data LVTTL
Output
OUTPUT
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
operation, test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction
Register, ID Register and Bypass Register. This output is high impedance except when shifting, while
in SHIFT-DR and SHIFT-IR controller states.
TMS⁽²⁾
(B8)
TRST⁽²⁾
(C7)
JTAG Mode
Select
JTAG Reset
LVTTL
INPUT
LVTTL
INPUT
TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the
device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically
reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK
cycles. If the TAP controller is not properly reset then the outputs will always be in high-impedance. If the
JTAG function is used but the user does not want to use TRST, then TRST can be tied with MRS to ensure
proper queue operation. If the JTAG function is not used then this signal needs to be tied to GND. An
internal pull-up resistor forces TRST HIGH if left unconnected.
WADEN
(P4)
WCLK
(T7)
WEN
(T6)
Write Address
Enable
Write Clock
Write Enable
LVTTL
INPUT
The WADEN input is used in conjunction with WCLK and the WRADD address bus to select a queue to
be written in to. A queue addressed via the WRADD bus is selected on the rising edge of WCLK provided
that WADEN is HIGH. WADEN should be asserted (HIGH) only during a queue cycle(s). WADEN should
not be permanently tied HIGH. WADEN cannot be HIGH for the same WCLK cycle as FSTR. Note, that
a write queue selection cannot be made, (WADEN must NOT go active) until programming of the part has
been completed and SENO has gone LOW.
HSTL-LVTTL
INPUT
When enabled by WEN, the rising edge of WCLK writes data into the selected queue via the input bus,
Din. The queue to be written to is selected via the WRADD address bus and a rising edge of WCLK while
WADEN is HIGH. A rising edge of WCLK in conjunction with FSTR and WRADD will also select the flag
quadrant to be placed on the PAFn bus during direct flag operation. During polled flag operation the PAFn
bus is cycled with respect to WCLK and the FSYNC signal is synchronized to WCLK. The PAFn, PAF and
FF outputs are all synchronized to WCLK. During device expansion the FXO and FXI signals are based
on WCLK. The WCLK must be continuous and free-running.
HSTL-LVTTL The WEN input enables write operations to a selected queue based on a rising edge of WCLK. A queue
INPUT to be written to can be selected via WCLK, WADEN and the WRADD address bus regardless of the state
of WEN. Data present on Din can be written to a newly selected queue on the second WCLK cycle after
queue selection provided that WEN is LOW. A write enable is not required to cycle the PAFn bus (in polled
mode) or to select the PAFn quadrant , (in direct mode).
WRADD
[4:0]
(WRADD4-T1
WRADD3-R1
WRADD2-R2
WRADD1-N1
WRADD0-N2)
Write Address
Bus
HSTL-LVTTL
INPUT
For the 4Q device the WRADD bus is 5 bits. The WRADD bus is a dual purpose address bus. The first
function of WRADD is to select a queue to be written to. The least significant 2 bits of the bus, WRADD[1:0]
are used to address 1 of 4 possible queues within a multi-queue device. The most significant 3 bits,
WRADD[4:2] are used to select 1 of 8 possible multi-queue devices that may be connected in expansion
mode. These 3 MSB’s will address a device with the matching ID code. The address present on the
WRADD bus will be selected on a rising edge of WCLK provided that WADEN is HIGH, (note, that data
present on the Din bus can be written into the previously selected queue on this WCLK edge and on the
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