IDT72264 Datasheet, PDF (10/31 Pages) Integrated Device Technology – VARIABLE WIDTH SUPERSYNCO FIFO 8,192 x 18 or 16,384 x 9 16,384 x 18 or 32,768 x 9

IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO™
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
OUTPUT ENABLE (OE)
When Output Enable is enabled (LOW), the parallel output
buffers receive data from the output register. When OE is
HIGH, the output data bus (Qn) goes into a high impedance
state.
LOAD (LD)
This is a dual purpose pin. During Master Reset, the state
of the LD input determines one of two default values (127 or
1023) for the PAE and PAF flags, along with the method by
which these flags can be programmed, parallel or serial. After
Master Reset, LD enables write operations to and read
operations from the registers. Only the offset loading method
currently selected can be used to write to the registers. Aside
from Master Reset, there is no other way change the loading
method. Registers can be read only in parallel; this can be
accomplished regardless of whether serial or the parallel
loading has been selected.
Associated with each of the programmable flags, PAE and
PAF, is one register which can either be written to or read from.
Offset values contained in these registers determine how
many words need to be in the FIFO memory to switch a partial
flag. A LOW on LD during Master Reset selects a default PAE
offset value of 07FH ( a threshold 127 words from the empty
boundary), a default PAF offset value of 07FH (a threshold 127
words from the full boundary), and parallel loading of other
offset values. A HIGH on LD during Master Reset selects a
default PAE offset value of 3FFH (a threshold 1023 words from
the empty boundary), a default PAF offset value of 3FFH (a
threshold 1023 words form the full boundary), and serial
loading of other offset values.
The act of writing offsets (in parallel or serial) employs a
dedicated write offset register pointer. The act of reading
offsets employs a dedicated read offset register pointer. The
two pointers operate independently; however, a read and a
write should not be performed simultaneously to the offset
registers. A Master Reset initializes both pointers to the
Empty Offset (LSB) register. A Partial Reset has no effect on
the position of these pointers.
It is important to note that the MAC setting configures the
offset register architecture to suit the memory array dimen-
sions being selected. Therefore, the way offsets are pro-
grammed will vary according to whether MAS is tied to Vcc or
GND.
Consider the case where serial offset loading has been
selected. If MAC = GND (18-bit operation), then programming
PAE and PAF proceeds as follows: When LD and SEN are set
LOW, data on the SI input are written, one bit for each WCLK
rising edge, starting with the Empty Offset (13 bits for the
72264, 14 bits for the 72274) and ending with the Full Offset
(13 bits for the 72264, 14 bits for the 72274). A total of 26 bits
are necessary to program the 72264; a total of 28 bits are
necessary to program the 72274.
If serial offset loading has been selected and MAC = Vcc
(9-bit operation), then programming PAE and PAF proceeds
as follows: When LD and SEN are set LOW, data on the SI
input are written, one bit for each WCLK rising edge, starting
with the Empty Offset LSB (8 bits for both the 72264 and
72274), then the Empty Offset MSB (6 bits for the 72264, 7 bits
for the 72274) , then the Full Offset LSB (8 bits for both the
72264 and 72274), ending with the Full Offset MSB (6 bits for
the 72264, 7 bits for the 72274). A total of 28 bits are
necessary to program the 72264; a total of 30 bits are
necessary to program the 72274.
For either MAC setting, individual registers cannot be
loaded serially; rather, all offsets must be programmed in
sequence, no padding allowed. PAE and PAF can show a
valid status only after the full set of bits have been entered.
The registers can be re-programmed as long as all offsets are
loaded. When LD is LOW and SEN is HIGH, no serial write to
the registers can occur.
Consider the case where parallel offset loading has been
selected. If MAC = GND (18-bit operation), then programming
PAE and PAF proceeds as follows: When LD and WEN are
set LOW, data on the inputs Dn are written into the Empty
Offset Register on the first LOW-to-HIGH transition of WCLK.
Upon the second LOW-to-HIGH transition of WCLK, data at
the inputs are written into the Full Register. The third transition
of WCLK writes, once again, to the Empty Offset Register.
If parallel offset loading has been selected and MAC = Vcc
(9-bit operation), then programming PAE and PAF proceeds
as follows: When LD and WEN are set LOW, data on the
inputs Dn are written into the LSB Empty Offset Register on the
first LOW-to-HIGH transition of WCLK. Upon the second
LOW-to-HIGH transition of WCLK, data at the inputs are
written into the MSB Empty Offset Register. Upon the third
LOW-to-HIGH transition of WCLK, data at the inputs are
written into the LSB Full Offset Register. Upon the fourth
LOW-to-HIGH transition of WCLK, data at the inputs are
written into the MSB Full Offset Register. The fifth transition of
WCLK writes, once again, to the LSB Empty Offset Register.
To ensure proper programming (serial or parallel) of the
offset registers, no read operation is permitted from the time
of reset (master or partial) to the time of programming. (During
this period, the read pointer must be pointing to the first
location of the memory array.) After the programming has
been accomplished, read operations may begin.
Write operations to memory are allowed before and during
the parallel programming sequence. In this case, the pro-
gramming of all offset registers does not have to occur at one
time. One or two offset registers can be written to and then,
by bringing LD HIGH, write operations can be redirected to the
FIFO memory. When LD is set LOW again, and WEN is LOW,
the next offset register in sequence is written to. As an
alternative to holding WEN LOW and toggling LD, parallel
programming can also be interrupted by setting LD LOW and
toggling WEN.
Write operations to memory are allowed before and during
the serial programming sequence. In this case, the program-
ming of all offset bits does not have to occur at once. A select
number of bits can be written to the SI input and then, by
bringing LD and SEN HIGH, data can be written to FIFO
memory via Dn by toggling WEN. When WEN is brought HIGH
with LD and SEN restored to a LOW, the next offset bit in
sequence is written to the registers via SI. If a mere interrup-
tion of serial programming is desired, it is sufficient either to set
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