IDT72264 Datasheet, PDF (1/31 Pages) Integrated Device Technology – VARIABLE WIDTH SUPERSYNCO FIFO 8,192 x 18 or 16,384 x 9 16,384 x 18 or 32,768 x 9

VARIABLE WIDTH SUPERSYNC™ FIFO
8,192 x 18 or 16,384 x 9
16,384 x 18 or 32,768 x 9
IDT72264
IDT72274
Integrated Device Technology, Inc.
FEATURES:
• Select 8192 x 18 or 16384x 9 organization (IDT72264)
• Select 16384 x 18 or 32678 x 9 organization (IDT72274)
• Flexible control of read and write clock frequencies
• Reduced dynamic power dissipation
• Auto power down minimizes power consumption
• 15 ns read/write cycle time (10 ns access time)
• Retransmit Capability
• Master Reset clears entire FIFO, Partial Reset clears
data, but retains programmable settings
• Empty, full and half-full flags signal FIFO status
• Programmable almost empty and almost full flags, each
flag can default to one of two preselected offsets
• Program partial flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or
First Word Fall Through timing (using OR and IR flags)
• Easily expandable in depth and width
• Independent read and write clocks (permits simultaneous
reading and writing with one clock signal)
• Available in the 64-pin Thin Quad Flat Pack (TQFP), 64-
pin Slim Thin Quad Flat Pack (STQFP) and the 68-pin
Pin Grid Array (PGA)
• Output enable puts data outputs into high impedance
• High-performance submicron CMOS technology
FUNCTIONAL BLOCK DIAGRAM
• Industrial temperature range (-40^OC to +85^OC) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT72264/72274 are monolithic, CMOS, high capac-
ity, high speed, low power first-in, first-out (FIFO) memories
with clocked read and write controls. These FIFOs have three
main features that distinguish them among SuperSync FIFOs:
First, the data path width can be changed from 9-bits to 18-
bits; as a result, halving the depth. A pin called Memory Array
Select (MAC) chooses between the two options. This feature
helps reduce the need for redesigns or multiple versions of PC
cards, since a single layout can be used for both data bus
widths.
Second, IDT72264/72274 offer the greatest flexibility for
setting and varying the read and write clock (WCLK and
RCLK) frequencies. For example, given that the two clock
frequencies are unequal, the slower clock may exceed the
faster by, at most, twice its frequency. This feature is espe-
cially useful for communications and network applications
where clock frequencies are switched to permit different data
rates.
WEN _WCLK
D0-Dn
LD SEN
•
•
INPUT REGISTER
OFFSET REGISTER
WRITE CONTROL
LOGIC
WRITE POINTER
MAC
MEMORY ARRAY
CONFIGURATION
••
RAM ARRAY
8192 x 18 or 16384 x 9
16384 x 18 or 32768 x 9
••
OUTPUT REGISTER
FLAG
LOGIC
READ POINTER
FPFA/_FIR
EF/OR
PAE
HF
FWFT/SI
READ
CONTROL
RT
LOGIC
MRS
RESET
•
PRS
LOGIC
•
RCLK
• REN
FS
TIMING
OE
Q0-Qn
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGES
3218 drw 01
©1997 Integrated Device Technology, Inc
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
MAY 1997
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