IDT70V07S_13 Datasheet, PDF (10/19 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM

IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side⁽¹⁾
tSAA
tOH
A0-A2
VALID ADDRESS
VALID ADDRESS
SEM
tAW
tWR
tEW
tACE
DATA0
R/W
tDW
tSOP
DATAIN VALID
tAS
tWP
tDH
DATAOUT
VALID⁽²⁾
tSWRD
tAOE
OE
Write Cycle
tSOP
Read Cycle
NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle).
2. “DATAOUT VALID” represents all I/O's (I/O0-I/O7) equal to the semaphore value.
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Timing Waveform of Semaphore Write Contention^(1,3,4)
A0"A"-A2"A"
MATCH
SIDE⁽²⁾ "A"
R/W"A"
SEM"A"
A0"B"-A2"B"
SIDE⁽²⁾ "B"
R/W"B"
tSPS
MATCH
SEM"B"
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NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/WB or SEM"B" going HIGH.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
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