IDT7015S_06 Datasheet, PDF (10/20 Pages) Integrated Device Technology – HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM

IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing^(1,5,8)
tWC
ADDRESS
tHZ ⁽⁷⁾
OE
tAW
CE or SEM⁽⁹⁾
tHZ ⁽⁷⁾
R/W
DATAOUT
DATAIN
tAS ⁽⁶⁾
tLZ
tWP⁽²⁾
tWZ ⁽⁷⁾
(4)
tWR⁽³⁾
tOW
tDH
tDW
(4)
,
2954 drw 09
Timing Waveform of Write Cycle No. 2, CE Controlled Timing^(1,5)
tWC
ADDRESS
(9)
CE or SEM
tAS⁽⁶⁾
tAW
tEW ⁽²⁾
tWR⁽³⁾
R/W
tDW
tDH
DATAIN
2954 drw 10
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified
tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access Semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
61.402
APRIL 04, 2006