IDT7015S_06 Datasheet, PDF (1/20 Pages) Integrated Device Technology – HIGH-SPEED 8K x 9 DUAL-PORT STATIC RAM

HIGH-SPEED
8K x 9 DUAL-PORT
STATIC RAM
IDT7015S/L
Features:
◆ _{True Dual-Ported memory cells which allow simultaneous}
reads of the same memory location
◆ _{High-speed access}
– Commercial: 12/15/17/20/25/35ns (max.)
– Industrial: 20ns (max.)
– Military: 20/25/35ns (max.)
◆ _{Low-power operation}
– IDT7015S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7015L
Active: 750mW (typ.)
Standby: 1mW (typ.)
◆ _{IDT7015 easily expands data bus width to 18 bits or more}
using the Master/Slave select when cascading more than
one device
Functional Block Diagram
◆ _{M/S = VIH for BUSY output flag on Master}
M/S = VIL for BUSY input on Slave
◆ _{Busy and Interrupt Flag}
◆ _{On-chip port arbitration logic}
◆ _{Full on-chip hardware support of semaphore signaling}
between ports
◆ _{Fully asynchronous operation from either port}
◆ _{TTL-compatible, single 5V (±10%) power supply}
◆ _{Available in ceramic 68-pin PGA, 68-pin PLCC, and an 80-}
pin TQFP
◆ _{Industrial temperature range (–40°C to +85°C) is available}
for selected speeds
◆ _{Green parts available, see ordering information}
OEL
CEL
R/WL
OER
CER
R/WR
I/O0L- I/O8L
BUSY_L^(1,2)
A12L
A0L
I/O
Control
I/O
Control
Address
Decoder
13
CEL
OEL
R/WL
MEMORY
ARRAY
13
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEML
INTL⁽²⁾
M/S
NOTES:
1. In MASTER mode: BUSY is an output and is a push-pull driver
In SLAVE mode: BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull drivers.
1
©2006 Integrated Device Technology, Inc.
Address
Decoder
I/O0R-I/O8R
BUSYR^(1,2)
A12R
A0R
CER
OER
R/WR
2954 drw 01
SEMR
INTR⁽²⁾
APRIL 2006
DSC 2954/7