8V97053L Datasheet, PDF (10/68 Pages) Integrated Device Technology – Low Power Wideband Fractional RF Synthesizer / PLL

8V97053L Datasheet
Reference Doubler
To improve the phase noise performance of the device, the reference doubler can be used. By using the doubler, the PFD frequency is also
doubled and the phase noise performance typically improves by 3dB. When operating the device in Fractional mode, the speed of the Sigma
Delta modulator of the N counter is limited to 125MHz, which is also the maximum PFD frequency that can be used in the fractional mode.
When the part operates in Integer-N mode, the PFD frequency is limited to 310MHz.
The user has the possibility to select a higher PFD frequency (up to 310MHz in Integer mode) by doing the following steps using the extended
registers (Register 6 and 7):
1. The user needs to increase the size of the Band Select Clock Divider (normally 8-bits) by setting the bit [D6:D3] in the Register 6 to divide
down to a frequency lower than 500kHz and higher than 125kHz.
2. Use the Bit[D27:D26] to increase the lock detect precision for the faster PFD frequency.
The Lock Detect window should be set as large as possible but less than a period of the phase detector. The phase detector frequency should
be greater than 500kHz.
Table 4A. Lock Detect Precision (LDP)
LDP_Ext2
(D27 of Register 6)
LDP_Ext1
(D26 of Register 6)
LDP
(D7 of Register 2)
0
0
0
0
0
1
Use of Extended Register 6
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
LDP value (ns)
10
6
3
3
4
4.5
1.5
1.5
©2016 Integrated Device Technology, Inc.
10
August 18, 2016