8SLVP2108_16 Datasheet, PDF (10/22 Pages) Integrated Device Technology – Low Phase Noise, Dual 1-to-8, 3.3V, 2.5V LVPECL Output Fanout Buffer

8SLVP2108 Datasheet
Applications Information
Wiring the Differential Input to Accept Single-Ended Levels
The 8SLVP2108 inputs can be interfaced to LVPECL, LVDS, CML or
LVCMOS drivers. Figure 1A illustrates how to DC couple a single
LVCMOS input to the 8SLVP2108. The value of the series resistance
RS is calculated as the difference between the transmission line
impedance and the driver output impedance. This resistor should be
placed close to the LVCMOS driver. To avoid cross-coupling of
single-ended LVCMOS signals, apply the LVCMOS signals to no
more than one PCLK input.
A practical method to implement Vth is shown in Figure 1B below.
The reference voltage Vth = V1 = V_CC/2, is generated by the bias
resistors R1 and R2. The bypass capacitor (C1) is used to help filter
noise on the DC bias. This bias circuit should be located as close to
the input pin as possible.
The ratio of R1 and R2 might need to be adjusted to position the V1
in the center of the input voltage swing. For example, if the input clock
swing is 2.5V and V_CC = 3.3V, R1 and R2 value should be adjusted
to set V1 at 1.25V. The values below apply when both the
single-ended swing and V_CC are at the same voltage.
V_IH
V_th
V_IL
RS
LVCMOS
V_th =
V_IH + V_IL
2
Figure 1A. DC-Coupling a Single LVCMOS Input to the
8SLVP2108
When using single-ended signaling, the noise rejection benefits of
differential signaling are reduced. Even though the differential input
can handle full rail LVCMOS signaling, it is recommended that the
amplitude be reduced, particularly if both input references are
LVCMOS to minimize cross talk. The datasheet specifies a lower
differential amplitude, however this only applies to differential signals.
For single-ended applications, the swing can be larger, however V_IL
cannot be less than -0.3V and V_IH cannot be more than V_CC + 0.3V.
Figure 1B shows a way to attenuate the PCLK input level by a factor
of two as well as matching the transmission line between the
LVCMOS driver and the 8SLVP2108 at both the source and the load.
This configuration requires that the sum of the output impedance of
the driver (Ro) and the series resistance (Rs) equals the transmission
line impedance. R3 and R4 in parallel should equal the transmission
line impedance; for most 50 applications, R3 and R4 will be 100.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver.
Though some of the recommended components of Figure 1B might
not be used, the pads should be placed in the layout so that they can
be utilized for debugging purposes. The datasheet specifications are
characterized and guaranteed by using a differential signal.
VCC
Ro
Driver
VCC
R3
100
RS
Zo = 50 Ohm
Ro + Rs = Zo
R4
100
C1
0.1uF
VCC
VCC
R1
1K
V1
R2
1K
+
Receiv er
-
Figure 1B. Alternative DC Coupling a Single LVCMOS Input to the 8SLVP2108
©2016 Integrated Device Technology, Inc.
10
Revision B, November 21, 2016