8SLVP2108_16 Datasheet, PDF (1/22 Pages) Integrated Device Technology – Low Phase Noise, Dual 1-to-8, 3.3V, 2.5V LVPECL Output Fanout Buffer

Low Phase Noise, Dual 1-to-8, 3.3V,
2.5V LVPECL Output Fanout Buffer
8SLVP2108
Datasheet
General Description
The 8SLVP2108 is a high-performance differential dual 1:8
LVPECL fanout buffer. The device is designed for the fanout of
high-frequency, very low additive phase-noise clock and data
signals. The 8SLVP2108 is characterized to operate from a 3.3V or
2.5V power supply. Guaranteed output-to-output and part-to-part
skew characteristics make the 8SLVP2108 ideal for those clock
distribution applications demanding well-defined performance and
repeatability. Two independent buffers with eight low skew outputs
each are available. The integrated bias voltage references enable
easy interfacing of single-ended signals to the device inputs. The
device is optimized for low power consumption and low additive
phase noise.
Block Diagram
V_CC
PCLKA
nPCLKA
V_REFA
Voltage
Reference
V_CC
PCLKB
nPCLKB
V_REFB
Voltage
Reference
QA0
nQA0
QA1
nQA1
QA2
nQA2








QA7
nQA7
QB0
nQB0
QB1
nQB1
QB2
nQB2








QB7
nQB7
Features
• Two 1:8, low skew, low additive jitter LVPECL fanout buffers
• Two differential clock inputs
• Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can
accept the following differential input levels: LVDS, LVPECL,
CML
• Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can
also accept single-ended LVCMOS levels. See Applications
section Wiring the Differential Input Levels to Accept
Single-ended Levels (Figure 1A and Figure 1B).
• Maximum input clock frequency: 2GHz
• Output bank skew: 15ps (typical)
• Propagation delay: 390ps (maximum)
• Low additive phase jitter, RMS: 54fs (maximum)
(f_REF = 156.25MHz, V_PP = 1V, 12kHz – 20MHz, V_CC = 3.3V)
• Full 3.3V and 2.5V supply voltage
• Maximum device current consumption (I_EE): 143mA
• Available in Lead-free (RoHS 6), 48-Lead VFQFN package
• Supports case temperature 105°C operations
• -40°C to 85°C ambient operating temperature
Pin Assignment
VCC
QB3
nQB3
QB4
nQB4
QB5
nQB5
QB6
nQB6
QB7
nQB7
VCC
36 35 34 33 32 31 30 29 28 27 26 25
37
24
38
23
39
22
40
8SLVP2108
21
41
48-lead VFQFN
20
42 _{7mm x 7mm x 0.8mm} 19
43
package body
18
44
45
NL Package
17
16
46
Top View
15
47
14
48
13
1 2 3 4 5 6 7 8 9 10 11 12
VCC
nQA4
QA4
nQA3
QA3
nQA2
QA2
nQA1
QA1
nQA0
QA0
VCC
©2016 Integrated Device Technology, Inc.
1
Revision B, November 21, 2016