8L30210 Datasheet, PDF (10/20 Pages) Integrated Device Technology – Crystal or Differential to LVCMOS/ LVTTL Clock Buffer

8L30210 DATA SHEET
Wiring the Differential Input to Accept Single-Ended Levels
Figure 2 shows how a differential input can be wired to accept single
ended levels. The reference voltage V_REF = V_DD/2 is generated by
the bias resistors R1 and R2. The bypass capacitor (C1) is used to
help filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the V_REF in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and V_DD = 3.3V,
R1 and R2 value should be adjusted to set V_REF at 1.25V. The values
below are for when both the single ended swing and V_DD are at the
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50 applications, R3 and R4 can be 100.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be reduced
while maintaining an edge rate faster than 1V/ns. The datasheet
specifies a lower differential amplitude, however this only applies to
differential signals. For single-ended applications, the swing can be
larger, however V_IL cannot be less than -0.3V and V_IH cannot be more
than V_DD + 0.3V. Though some of the recommended components
might not be used, the pads should be placed in the layout. They can
be utilized for debugging purposes. The datasheet specifications are
characterized and guaranteed by using a differential signal.
Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
Crystal Input Interface
The 8L30210 has been characterized with 12pF parallel resonant
crystals. The capacitor values, C1 and C2, shown in Figure 3 below
were determined using an 12pF parallel resonant crystal and were
chosen to minimize the ppm error. The optimum C1 and C2 values
can be slightly adjusted for different board layouts.
X1
12pF Parallel Crystal
C1
12pF
XTAL_IN
C2
12pF
XTAL_OUT
Figure 3. Crystal Input Interface
CRYSTAL OR DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK BUFFER
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REVISION 2 11/24/15