IDT70V9199L_10 Datasheet, PDF (1/17 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 128K x9/x8 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

HIGH-SPEED 3.3V
128K x9/x8
SYNCHRONOUS PIPELINED
Š _{DUAL-PORT STATIC RAM}
IDT70V9199/099L
Features:
◆ _{True Dual-Ported memory cells which allow simultaneous}
access of the same memory location
◆ _{High-speed clock to data access}
– Commercial: 9/12ns (max.)
– Industrial: 9ns (max.)
◆ _{Low-power operation}
– IDT70V9199/099L
Active: 500mW (typ.)
Standby: 1.5mW (typ.)
◆ _{Flow-Through or Pipelined output mode on either port via}
the FT/PIPE pins
◆ _{Dual chip enables allow for depth expansion without}
additional logic
◆ _{Counter enable and reset features}
◆ _{Full synchronous operation on both ports}
– 4ns setup to clock and 1ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 9 ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 15ns cycle time, 66 MHz operation in Pipelined output mode
◆ _{LVTTL- compatible, single 3.3V (±0.3V) power supply}
◆ _{Industrial temperature range (–40°C to +85°C) is}
available for selected speeds
◆ _{Available in a 100-pin Thin Quad Flatpack (TQFP)}
◆ _{Green parts available, see ordering information}
Functional Block Diagram
R/WL
OEL
CE0L
1
CE1L
0
0/1
R/WR
OER
CE0R
1
CE1R
0
0/1
FT/PIPEL
I/O0L - I/O8L(1)
0/1 ¹
0
I/O
Control
I/O
Control
0
1 _0/1
FT/PIPER
I/O0R - I/O8R(1^.)
A16L
A0L
CLKL
ADSL
CNTENL
CNTRSTL
NOTE:
1. I/O0X - I/O7X for IDT70V9099.
Counter/
Address
Reg.
©2010 Integrated Device Technology, Inc.
MEMORY
ARRAY
1
Counter/
Address
Reg.
A16R
A0R
CLKR
ADSR
CNTENR
CNTRSTR
4859 drw 01
JULY 2010
DSC-4859/7