IDT70V26S Datasheet, PDF (1/17 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM

HIGH-SPEED 3.3V
16K x 16 DUAL-PORT
STATIC RAM
IDT70V26S/L
Features
x _{True Dual-Ported memory cells which allow simultaneous}
reads of the same memory location
x _{High-speed access}
– Commercial: 25/35/55ns (max.)
x _{Low-power operation}
– IDT70V26S
Active: 300mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V26L
Active: 300mW (typ.)
Standby: 660µW (typ.)
x _{Separate upper-byte and lower-byte control for multiplexed}
bus compatibility
x _{IDT70V26 easily expands data bus width to 32 bits or more}
using the Master/Slave select when cascading more than
one device
x _{M/S = VIH for BUSY output flag on Master}
M/S = VIL for BUSY input on Slave
x _{On-chip port arbitration logic}
x _{Full on-chip hardware support of semaphore signaling}
between ports
x _{Fully asynchronous operation from either port}
x _{TTL-compatible, single 3.3V (±0.3V) power supply}
x _{Available in 84-pin PGA and PLCC}
x _{Industrial temperature range (-40°C to +85°C) is available}
for selected speeds
Functional Block Diagram
R/WL
UBL
R/WR
UBR
LBL
CEL
OEL
I/O8L-I/O15L
I/O0L-I/O7L
BUSYL^(1,2)
A13L
A0L
I/O
Control
I/O
Control
Address
Decoder
14
CEL
MEMORY
ARRAY
ARBITRATION
SEMAPHORE
LOGIC
Address
Decoder
14
CER
SEML
M/S
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs are non-tri-stated push-pull.
1
©2000 Integrated Device Technology, Inc.
LBR
CER
OER
I/O8R-I/O15R
I/O0R-I/O7R
BUSYR(1,2)
A13R
A0R
SEMR
2945 drw 01
JUNE 2000
DSC 2945/13