IDT5T9304 Datasheet, PDF (1/15 Pages) Integrated Device Technology – LVDS, 1:4 Clock Buffer Terabuffer™

LVDS, 1:4 Clock Buffer Terabuffer™
IDT5T9304
DATA SHEET
General Description
The IDT5T9304 differential clock buffer has a user-selectable
differential input to four LVDS outputs. The fanout from a differential
input to four LVDS outputs reduces loading on the preceding driver
and provides an efficient clock distribution network. The IDT5T9304
can act as a translator from a differential HSTL, eHSTL, LVEPECL
(2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A
single-ended 3.3V / 2.5V LVTTL input can also be used to translate
to LVDS outputs. The redundant input capability allows for an
asynchronous change-over from a primary clock source to a
secondary clock source. Selectable reference inputs are controlled
by SEL.
The IDT5T9304 outputs can be asynchronously enabled/disabled.
When disabled, the outputs will drive to the value selected by the GL
pin. Multiple power and grounds reduce noise.
Features
• Guaranteed low skew: 50ps (maximum)
• Very low duty cycle distortion: 125ps (maximum)
• Propagation delay: 1.75ns (maximum)
• Up to 450MHz operation
• Selectable inputs
• Hot insertable and over-voltage tolerant inputs
• 3.3V/2.5V LVTTL, HSTL eHSTL, LVEPECL (2.5V),
LVPECL (3.3V), CML or LVDS input interface
• Selectable differential inputs to four LVDS outputs
• 2.5V V_DD
• 0°C to 70°C ambient operating temperature
• Available in standard (RoHS 5) and lead-free (RoHS 6) packages
Applications
• Clock distribution
Pin Assignment
GND 1
PD 2
RESERVED 3
V_DD 4
Q1 5
Q1 6
Q2 7
Q2 8
VDD 9
SEL 10
G 11
GND 12
24 A2
23 A2
22 GND
21 VDD
20 Q3
19 Q3
18 Q4
17 Q4
16 VDD
15 GL
14 A1
13 A1
IDT5T9304
24-Lead TSSOP
4.4mm x 7.8mm x 1.0mm package body
G Package
Top View
IDT5T9304 REVISION A JANUARY 21, 2010
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©2010 Integrated Device Technology, Inc.