ICS9DB202_06 Datasheet, PDF (1/13 Pages) Integrated Device Technology – PCI EXPRESS JITTER ATTENUATOR

PCI EXPRESS JITTER ATTENUATOR
ICS9DB202
GENERAL DESCRIPTION
FEATURES
ICS
The ICS9DB202 is a high perfromance 1-to-2
HiPerClockS™ ^{Differential-to-HCSL Jitter Attenuator designed for}
use in PCI Express™ systems. In some PCI
Express™ systems, such as those found in desktop
PCs, the PCI Express™ clocks are generated from
a low bandwidth, high phase noise PLL frequency synthesizer.
In these systems, a jitter-attenuating device may be necessary
in order to reduce high frequency random and deterministic
jitter components from the PLL synthesizer and from the system
board. The ICS9DB202 has two PLL bandwidth modes. In low
bandwidth mode, the PLL loop bandwidth is 500kHz. This setting
offers the best jitter attenuation and is still high enough to pass
a triangular input spread spectrum profile. In high bandwidth
mode, the PLL bandwidth is at 1MHz and allows the PLL to
pass more spread spectrum modulation.
• Two 0.7V current mode differential HCSL output pairs
• One differential clock input
• CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum output frequency: 140MHz
• Input frequency range: 90MHz - 140MHz
• VCO range: 450MHz - 700MHz
• Output skew: 110ps (maximum)
• Cycle-to-cycle jitter: 110ps (maximum)
• RMS phase jitter @ 100MHz, (1.5MHz - 22MHz):
2.42ps (typical)
For serdes which have x10 reference multipliers instead of x12.5
multipliers, each of the two PCI Express™ outputs (PCIEX0:1)
can be set for 125MHz instead of 100MHz by configuring the
appropriate frequency select pins (FS0:1).
BLOCK DIAGRAM
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
• Industrial temperature information available upon request
IREF
+-
nOE0
Current
Set
1 HiZ
0 Enabled
nCLK
CLK
Phase
Detector
Loop
Filter
VCO
÷5
Internal Feedback
BYPASS
0
0 ÷4
1 ÷5
1
FS0
0
0 ÷5
1 ÷4
1
FS1
PCIEXT0
nPCIEXC0
PCIEXT1
nPCIEXC1
PIN ASSIGNMENT
PLL_BW 1
CLK 2
nCLK 3
FS0 4
VDD 5
GND 6
PCIEXT0 7
PCIEXC0 8
VDD 9
nOE0 10
20 VDDA
19 BYPASS
18 IREF
17 FS1
16 VDD
15 GND
14 PCIEXT1
13 PCIEXC1
12 VDD
11 nOE1
ICS9DB202
20-Lead TSSOP
6.50mm x 4.40mm x 0.92
package body
G Package
Top View
ICS9DB202
20-Lead, 209-MIL SSOP
5.30mm x 7.20mm x 1.75mm
body package
F Package
Top View
nOE1
1 HiZ
0 Enabled
IDT^™ / ICS^™ PCI EXPRESS JITTER ATTENUATOR
1
ICS9DB202CG REV B JULY 14, 2006