ICS9DB102 Datasheet, PDF (1/13 Pages) Integrated Circuit Systems – 2 Output PCI Express Buffer with CLKREQ Function

2 Output PCI Express* Buffer with CLKREQ# Function
DATASHEET
ICS9DB102
Description
1-to-2 Zero-delay or fanout buffer for PCI Express.The
ICS9DB102 zero-delay buffer supports PCI Express clocking
requirements. The ICS9DB102 is driven by a differential SRC
output pair from an ICS CK409/CK410-compliant main clock
generator such as the ICS952601 or ICS954101. It attenuates
jitter on the input clock and has a selectable PLL Band Width to
maximize performance in systems with or without Spread-
Spectrum clocking.
Output Features
• 2 - 0.7V current mode differential output pairs (HSCL)
Features/Benefits
• CLKREQ# pin for outputs 1 and 4/output enable for Express
Card applications
• PLL or bypass mode/PLL can dejitter incoming clock
• Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL’s
• Spread Spectrum Compatible/tracks spreading input clock
for low EMI
• SMBus Interface/unused outputs can be disabled
Key Specifications
• Cycle-to-cycle jitter < 35ps
• Output-to-output skew < 25ps
Funtional Block Diagram
CLKREQ0#
CLKREQ1#
CLK_INT
C LK_IN C
PLL_BW
SMBDAT
SMBCLK
SPREAD
COMPATIBLE
PLL
CONTROL
LOGIC
PCIEX0
PCIEX1
IREF
IDT^TM/ICS^TM 2 Output Express* Buffer with CLKREQ# Function
1
ICS9DB102 REV F 08/06/07