ICS93V855I Datasheet, PDF (1/9 Pages) Integrated Device Technology – Spread Spectrum tolerant inputs

DDR Phase Lock Loop Clock Driver
Recommended Application:
DDR Clock Driver
• Low skew, low jitter PLL clock driver
• External feedback pins for input to output
synchronization
• Spread Spectrum tolerant inputs
• With bypass mode mux
• Operating frequency 60 to 170 MHz
• Operating Temperature –45°C to +85°C
• CYCLE - CYCLE jitter:<75ps
• OUTPUT - OUTPUT skew: <60ps
• Output Rise and Fall Time: 650ps - 950ps
ICS93V855I
Block Diagram
Control
Logic
FB_INT
FB_INC
CLK_INC
PLL
CLK_INT
AVDD2.5
0783C—06/01/04
Functionality
FB_OUTT
FB_OUTC
DDRT0
DDRC0
DDRT1
DDRC1
DDRT2
DDRC2
DDRT3
DDRC3
DDRT4
DDRC4
INPUTS
AVDD CLK_INT CLK_INC DDRT
GND
L
H
L
GND H
L
H
2.5V
(nom)
L
H
L
2.5V
(nom)
H
L
H
2.5V
(nom)
<20 MHz
<20 MHz
Hi-Z
OUTPUTS
DDRC FB_OUTT FB_OUTC
H
L
H
L
H
L
H
L
H
L
H
L
Hi-Z
Hi-Z
Hi-Z
PLL State
Bypassed/Off
Bypassed/Off
On
On
Off