ICS8S89834I Datasheet, PDF (1/17 Pages) Integrated Device Technology – Low Skew, 2-to-4 LVCMOS/LVTTL-to-LVPECL/ECL Clock Multiplexer

Low Skew, 2-to-4 LVCMOS/LVTTL-to-
LVPECL/ECL Clock Multiplexer
ICS8S89834I
DATA SHEET
General Description
The ICS8S89834I is a high speed 2-to-4
ICS
LVCMOS/LVTTL-to-LVPECL/ECL Clock Multiplexer.
HiPerClockS™ _{The ICS8S89834I is optimized for high speed and very}
low output skew, making it suitable for use in
demanding applications such as SONET, 1 Gigabit
and 10 Gigabit Ethernet, and Fibre Channel. The device also has an
output enable pin which may be useful for system test and debug
purposes. The ICS8S89834I is packaged in a small 3mm x 3mm
16-pin VFQFN package which makes it ideal for use in
space-constrained applications.
Features
• Four differential LVPECL/ECL output pairs
• Two LVCMOS/LVTTL clock inputs
• Maximum output frequency: 1GHz
• Output skew: 30ps (maximum)
• Part-to-part skew: 100ps (maximum)
• Propagation delay: 550ps (maximum)
• Additive phase jitter, RMS: 0.12ps (typical)
• Full 3.3V and 2.5V operating supply modes
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Block Diagram
SEL ^Pullup
IN1 ^Pullup
1
0
IN2 ^Pullup
EN ^Pullup
DQ
CK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Pin Assignment
16 15 14 13
Q1 1
12 IN1
nQ1 2
11 SEL
Q2 3
10 nc
nQ2 4
9 IN2
5 6 78
ICS8S89834I
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
K Package
Top View
ICS8S89834AKI REVISION A FEBRUARY 4, 2010
1
©2010 Integrated Device Technology, Inc.