ICS853S9252I Datasheet, PDF (1/21 Pages) Integrated Device Technology – 2.5V, 3.3V ECL/LVPECL Clock/Data Fanout Buffer

2.5V, 3.3V ECL/LVPECL Clock/Data
Fanout Buffer
ICS853S9252I
DATASHEET
General Description
The ICS853S9252I is a 2.5V/3.3V ECL/LVPECL fanout buffer
designed for high-speed, low phase-noise wireless infrastructure
applications. The device fanouts a differential input signal to two
ECL/LVPECL outputs. Optimized for low additive phase-noise,
sub-100ps output rise and fall times, low output skew and
high-frequencies, the ICS853S9252I is an effective solution for
high-performance clock and data distribution applications, for
instance driving the reference clock inputs of ADC/DAC circuits.
Internal input termination, a bias voltage output (V_REF) for
AC-coupling and small packaging (3.0mm x 3.0mm 16-lead VFQFN)
supports space-efficient board designs.
The ICS853S9252I operates from a full 2.5V or 3.3V power supply
and supports the industrial temperature range of -40°C to 85°C. The
extended temperature range also supports wireless infrastructure,
tele-communication and networking end equipment requirements.
Features
• 1:2 differential clock/data fanout buffer
• Clock frequency: 3GHz (maximum)
• Two differential 2.5V/3.3V ECL/LVPECL clock output
• Differential input accepts ECL/LVPECL, LVDS and CML levels
• Additive phase jitter, RMS @ 122.88MHz: 45fs (typical)
• Propagation delay: 175ps (maximum), V_CC = 3.3V
• Output rise/fall time: 135ps (maximum), V_CC = 3.3V
• Internal input signal termination
• Supply voltage: 2.5V-5% to 3.3V+10%
• Lead-free (RoHS 6) packaging
• -40°C to 85°C ambient operating temperature
Block Diagram
IN
nIN
50
VTT
VREF
50
VREF
Generator
Pin Assignment
Q0
nQ0
Q1
nQ1
16 15 14 13
IN 1
12 Q0
nIN 2
11 nQ0
nc 3
10 Q1
nc 4
9 nQ1
56 7 8
ICS853S9252I
16 lead VFQFN
3.0mm x 3.0mm x 0.925mm
package body
K Package
Top View
ICS853S9252BKI JUNE 14, 2017
1
©2017 Integrated Device Technology, Inc.