ICS570 Datasheet, PDF (1/11 Pages) Integrated Circuit Systems – Multiplier and Zero Delay Buffer

MULTIPLIER AND ZERO DELAY BUFFER
DATASHEET
ICS570
Description
The ICS570 is a high-performance Zero Delay Buffer (ZDB)
which integrates IDT’s proprietary analog/digital Phase
Locked Loop (PLL) techniques. The A version is
recommended for 5 V designs and the B version for
3.3 V designs. The chip is part of IDT’s ClockBlocks^TM
family, and was designed as a performance upgrade to
meet today’s higher speed and lower voltage requirements.
The zero delay feature means that the rising edge of the
input clock aligns with the rising edges of both output
clocks, giving the appearance of no delay through the
device. There are two outputs on the chip, one being a
low-skew divide by two of the other output. The device
incorporates an all-chip power down/tri-state mode that
stops the internal PLL and puts both outputs into a high
impedance state.
The ICS570 is ideal for synchronizing outputs in a large
variety of systems, from personal computers to data
communications to graphics/video. By allowing off-chip
feedback paths, the device can eliminate the delay through
other devices.
The ICS570 A and B versions were designed to improve
input to output jitter from the original ICS570M version, and
are recommended for all new designs.
Features
• 8-pin SOIC package
• Available in Pb (lead) free package
• Pin-for-pin replacement and upgrade to ICS570M
• Functional equivalent to AV9170 (not a pin-for-pin
replacement)
• Low input to output skew of 300 ps max (>60 MHz
outputs)
• Ability to choose between 14 different multipliers from
0.5x to 32x
• Output clock frequency up to 170 MHz at 3.3 V
• Can recover degraded input clock duty cycle
• Output clock duty cycle of 45/55
• Power Down and Tri-State Mode
• Passes spread spectrum clock modulation
• Full CMOS clock swings with 25 mA drive capability at
TTL levels
• Advanced, low power CMOS process
• ICS570B has an operating voltage of 3.3 V (±5%)
• ICS570A has an operating voltage of 5.0 V (±5%)
• Industrial temperature version available
Block Diagram
IC L K
S 1 :0
F B IN
divide
by N
Phase
D e te c to r,
C ha rg e
Pum p,
and Loop
F ilte r
VCO
/2
CLK
CLK2
External feedback can com e from C LK or C LK/2 (see table on page 2)
IDT™ / ICS™ MULTIPLIER AND ZERO DELAY BUFFER
1
ICS570
REV K 073007