9DBU0241 Datasheet, PDF (1/17 Pages) Integrated Circuit Systems – slew rate for each output

2 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
w/Zo=100ohms
9DBU0241
DATASHEET
Description
The 9DBU0241 is a member of IDT's 1.5V Ultra-Low-Power
(ULP) PCIe family. It has integrated output terminations
providing Zo=100ohms for direct connection to 100ohm
transmission lines. The device has 2 output enables for clock
management.
Recommended Application
1.5V PCIe Gen1-2-3 Zero-Delay/Fan-out Buffer (ZDB/FOB)
Output Features
• 2 – 1-167MHz Low-Power (LP) HCSL DIF pairs
w/ZO=100
Key Specifications
• DIF cycle-to-cycle jitter <50ps
• DIF output-to-output skew <50ps
• DIF phase jitter is PCIe Gen1-2-3 compliant
• DIF bypass mode additive phase jitter is <300fs rms for
PCIe Gen3
• DIF bypass mode additive phase jitter <350fs rms for
12k-20MHz
Block Diagram
Features/Benefits
• Direct connection to 100 transmission lines; saves 8
resistors compared to standard HCSL outputs
• 35mW typical power consumption in PLL mode; eliminates
thermal concerns
• Spread Spectrum (SS) compatible; allows SS for EMI
reduction
• OE# pins; support DIF power management
• HCSL-compatible differential input; can be driven by
common clock sources
• SMBus-selectable features; optimize signal integrity to
application
• slew rate for each output
• differential output amplitude
• Pin/SMBus selectable PLL bandwidth and PLL Bypass;
optimize PLL to application
• Outputs blocked until PLL is locked; clean system start-up
• Device contains default configuration; SMBus interface not
required for device control
• 3.3V tolerant SMBus interface works with legacy controllers
• Space saving 24-pin 4x4mm VFQFPN; minimal board
space
vOE(1:0)#
2
CLK_IN
CLK_IN#
SS-
Compatible
PLL
DIF1
DIF0
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
9DBU0241 REVISION C 04/22/15
1
©2015 Integrated Device Technology, Inc.