89HPES24T6G2 Datasheet, PDF (1/54 Pages) Integrated Device Technology – Support for Max Payload Size up to 2048 bytes

24-Lane 6-Port
Gen2 PCI Express® Switch
®
89HPES24T6G2
Data Sheet
Device Overview
The 89HPES24T6G2 is a member of IDT’s PRECISE™ family of PCI
Express® switching solutions. The PES24T6G2 is a 24-lane, 6-port
Gen2 peripheral chip that performs PCI Express base switching with a
feature set optimized for high performance applications such as servers,
storage, and communications systems. It provides connectivity and
switching functions between a PCI Express upstream port and up to five
downstream ports and supports switching between downstream ports.
Features
 _{High Performance PCI Express Switch}
– Twenty-four 5 Gbps Gen2 PCI Express lanes supporting
5 Gbps and 2.5 Gbps operation
– Up to six switch ports
– Support for Max Payload Size up to 2048 bytes
– Supports one virtual channel and eight traffic classes
– Fully compliant with PCI Express base specification Revision
2.0
 _{Flexible Architecture with Numerous Configuration Options}
– Automatic per port link width negotiation to x8, x4, x2, or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion
– Supports in-band hot-plug presence detect capability
– Supports external signal for hot plug event notification allowing
SCI/SMI generation for legacy operating systems
– Dynamic link width reconfiguration for power/performance
optimization
– Configurable downstream port PCI-to-PCI bridge device
numbering
– Crosslink support
– Supports ARI forwarding defined in the Alternative Routing-ID
Interpretation (ARI) ECN for virtualized and non-virtualized
environments
– Ability to load device configuration from serial EEPROM
 _{Legacy Support}
– PCI compatible INTx emulation
– Supports bus locked transactions, allowing use of PCI Express
with legacy software
 _{Highly Integrated Solution}
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates twenty-four 5 Gbps / 2.5 Gbps embedded SerDes,
8B/10B encoder/decoder (no separate transceivers needed)
 _{Reliability, Availability, and Serviceability (RAS) Features}
– Ability to disable peer-to-peer communications
– Supports ECRC and Advanced Error Reporting
– All internal data and control RAMs are SECDED ECC
protected
– Supports PCI Express hot-plug on all downstream ports
– Supports upstream port hot-plug
Block Diagram
Frame Buffer
6-Port Switch Core / 24 Gen2 PCI Express Lanes
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
Phy
Logical
Layer
SerDes
(Port 0)
(Port 1)
Figure 1 Internal Block Diagram
 2013 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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(Port 5)
April 30, 2013
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