8735-31 Datasheet, PDF (1/21 Pages) Integrated Device Technology – Selectable differential clock inputs

1:5, Differential-to-3.3V LVPECL Zero
Delay Clock Generator
8735-31
DATA SHEET
General Description
The 8735-31 is a highly versatile 1:5 Differential -to-3.3V LVPECL
Clock Generator. The 8735-31 has a fully integrated PLL and can
be configured as zero delay buffer, multiplier or divider, and has an
output frequency range of 15.625MHz to 350MHz. The reference
divider, feedback divider and output divider are each
programmable, thereby allowing for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external
feedback allows the device to achieve “zero delay” between the
input clock and the output clocks. The PLL_SEL pin can be used
to bypass the PLL for system test and debug purposes. In bypass
mode, the reference clock is routed around the PLL and into the
internal output dividers.
Features
• Five differential 3.3V LVPECL output pairs
• Selectable differential clock inputs
• CLKx/nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Output frequency range: 15.625MHz to 350MHz
• Input frequency range: 15.625MHz to 350MHz
• VCO range: 250MHz to 700MHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Cycle-to-cycle jitter: 60ps (maximum)
• Output skew: 35ps (maximum)
• Static phase offset: 55ps ± 125ps
• Full 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
PLL_SEL ^Pullup
CLK0 ^Pulldown
nCLK0 ^Pullup
CLK1 ^Pulldown
nCLK1 ^Pullup
CLK_SEL ^Pulldown
FB_IN ^Pulldown
nFB_IN ^Pullup
÷2, ÷4, ÷8, ÷16,
0
÷32,÷64, ÷128
0
1
1
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
SEL0 ^Pulldown
SEL1 ^Pulldown
SEL2 ^Pulldown
SEL3 ^Pulldown
MR ^Pulldown
8735-31 Rev B 7/16/15
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
1
Pin Assignment
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
32 31 30 29 28 27 26 25
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9 10 11 12 13 14 15 16
VCCO
Q3
nQ3
Q2
nQ2
Q1
nQ1
VCCO
8735-31
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
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