79RC32T336-150BCG Datasheet, PDF (1/44 Pages) Integrated Device Technology – IDTTM InterpriseTM Integrated Communications Processor

IDT^TM Interprise^TM Integrated
Communications Processor
RC32336
Device Overview
The RC32336 device is a member of the IDT™ Interprise™ family of
integrated communications processors. It provides an effective solution
for small office/home office (SOHO) applications including gateways and
both single-band and dual-band wireless access points. Featuring a
MIPS compatible CPU core, the device also includes a memory
controller supporting SDRAM memory, a PCI interface featuring an on-
chip arbiter to support up to three external devices, a PCMCIA interface
that supports a single I/O device, and two integrated on-chip 10/100
Ethernet MACs to enable WAN and LAN connectivity.
The key features of the RC32336 enable SOHO applications at
unmatched price/performance points. The MIPS-compatible CPU core
has the required bandwidth to enable a WAP application with the latest
wireless security protocols, WPA and 802.11i, which include the enter-
prise-level user authentication schemes 802.1x and Extensible Authenti-
cation Protocol (EAP). The ability to connect and support the bandwidth
requirements of one or two WLAN modules is made possible by the high
bandwidth PCI and PCMCIA interfaces. Also, the device has been archi-
tected to provide high speed LAN to WAN routing bandwidth through the
Ethernet MACs while simultaneously driving data through the other on-
chip interfaces.
Features List
x _{RC32300 32-bit CPU core}
– 32-bit MIPS instruction set
– Supports big or little endian operation
– MMU
– 16-entry TLB
– Supports variable page sizes and enhanced write algo-
rithm
– Supports variable number of locked entries
– 8KB Instruction Cache
– 2-way set associative
– LRU replacement algorithm
– 4 word line size
– Sub-block ordering
– Word parity
– Per line cache locking
– 2KB Data Cache
– 2-way set associative
– LRU replacement algorithm
– 4 word line size
– Sub-block ordering
– Byte parity
– Per line cache locking
– Can be programmed on a page basis to implement write-
through no write allocate, write-through write allocate, or
write-back algorithms
– Enhanced EJTAG and JTAG Interfaces
– Compatible with IEEE Std. 1149.1-1990
Block Diagram
SPI Bus
MII MII
MIPS-32
CPU Core
EJTAG
MMU
D. Cache I. Cache
Interrupt
.
Controller _.
Bus/System
Integrity
Monitor
SPI
Controller
2 Ethernet
10/100
Interfaces
DMA
Controller
SDRAM &
Device
Controllers
3 Counter
Timers
IPBus^TM
UART
(16550)
GPIO
Interface
Arbiter
PCI
Master/Target
Interface
PCI Arbiter
(Host Mode)
Memory &
Peripheral Bus
(including PCMCIA)
Serial Channel
GPIO Pins
PCI Bus
Figure 1 RC32336 Internal Block Diagram
 2005 Integrated Device Technology, Inc.
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
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October 4, 2005
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