ICS84427 Datasheet, PDF (9/13 Pages) Integrated Circuit Systems – CRYSTAL-TO-LVDS INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS84427
CRYSTAL-TO-LVDS
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER
SCHEMATIC EXAMPLE
Figure 4A shows a schematic example of using an ICS84427. In
this example, the input is a 25MHz parallel resonant crystal with
load capacitor CL=18pF. The frequency fine tuning capacitors
C1 and C2 is 22pF and 18pF respectively. This example also
shows logic control input handling. The configuration is set at
F_SEL[2:0]=101, therefore, the output frequency is 156.25MHz.
It is recommended to have one decouple capacitor per power
pin. Each decoupling capacitor should be located as close as
possible to the power pin. The low pass filter R7, C11 and C16 for
clean analog supply should also be located as close to the VDDA
pin as possible. For LVDS driver, the unused output pairs should
be terminated with a 100Ω resistor across.
VDD
VDD
R7
24
C 11
0.1u
C16
10u
VDD
VDD
VDDA
22p
C1
X1
25MH z, 18pF
C2
18p
R4 VDD
1K
F_SEL2
F_SEL1
R5 F_SEL0
1K
U1
13
14
15
VDD
VEE
16 ^PLL_SEL
17
18
19
20
21
22
23
24
VDD
VDDA
F_SEL2
XTAL_OUT
XTAL_IN
MR
F_SEL1
F_SEL0
VDD
ICS84427
nQ5
Q5
12
11
10
nQ4 ₉
Q4
nQ3
Q3
nQ2
Q2
nQ1
Q1
nQ0
8
7
6
5
4
3
2
1
Q0
Zo = 50
R1
100
Zo = 50
RU1
1K
RU2
SP
RU3
1K
F_SEL2
F_SEL1
F_SEL0
VDD=3.3V
VD D
(U 1, 13)
(U 1, 16)
(U 1, 24)
RD1
SP
RD2
1K
RD3
SP
e.g. F_SEL[2:0]=101
SP = Spare, Not Installed
C6
0.1u
C5
0. 1u
C3
0.1u
+
-
LVDS_input
FIGURE 4A. ICS84427 SCHEMATIC EXAMPLE
84427CM
www.icst.com/products/hiperclocks.html
9
REV. D NOVEMBER 30, 2005