ICS844031I-01 Datasheet, PDF (9/12 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844031I-01
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
APPLICATION SCHEMATIC
Figure 4A provides a schematic example of ICS844031I. In this
example, an 18 pF parallel resonant crystal is used. The
C1=22pF and C2=22pF are recommended for frequency. The
C1 and C2 values may be slightly adjusted for optimizing fre-
quency accuracy. At least one decoupling capacitor near the
power pin is required. Suggested value range is from 0.01uF to
0.1uF. Other filter type can be added depending on the system
power supply noise type.
VDD
R2
10 C3
10uF
VDDA
C4
0.01u
U1
C2
22pF
X1
CL=18pF
C1
22pF
1
2
VCCA
3
4
GND
XTAL_OUT
XTAL_IN
ICS844031
VDD= 3.3V or 2.5V
VDD
8
7
Q0
nQ0
OE
6
5
VDD
R1
1K
VDD
C5
0.1u
Zo = 50 Ohm
R3
100
Zo = 50 Ohm
+
-
LVDS
FIGURE 4A. APPLICATION SCHEMATIC EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 4B shows an example of ICS844031I P.C. board layout.
The crystal X1 footprint shown in this example allows installa-
tion of either surface mount HC49S or through-hole HC49 pack-
age.The footprints of other components in this example are listed
in the Table 6. There should be at least one decoupling capacitor
per power pin. The decoupling capacitors should be located as
close as possible to the power pins. The layout assumes that
the board has clean analog power ground plane.
TABLE 6. FOOTPRINT TABLE
Reference
Size
C1, C2
0402
C3
0805
C4, C5
0603
R2
0603
NOTE: Table 6, lists component
sizes shown in this layout example.
FIGURE 4B. ICS843001 PC BOARD LAYOUT EXAMPLE
844031AGI-01
www.icst.com/products/hiperclocks.html
8
REV. B JULY 6, 2005