ICS844031I-01 Datasheet, PDF (7/12 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844031I-01
FEMTOCLOCKS™CRYSTAL-TO- LVDS
CLOCK GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844031I-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V and V should
DD
DDA
be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each V_DDA pin.
V_DD
V_DDA
3.3V or 2.5V
.01μF 10 Ω
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS844031I-01 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The optimum C1 and C2 values can be slightly adjusted for dif-
ferent board layouts.
X1
18pF Parallel Crystal
XTAL_OUT
C1
33p
XTAL_IN
C2
27p
Figure 2. CRYSTAL INPUt INTERFACE
844031AGI-01
www.icst.com/products/hiperclocks.html
7
REV. B JULY 6, 2005