ICS844004I-04 Datasheet, PDF (9/13 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-LVDS FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844004I-04
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
LVDS FREQUENCY SYNTHESIZER
SCHEMATIC EXAMPLE
Figure 4 shows a schematic example for ICS844004i-04. In this
example, the input is a 19.44MHz parallel resonant crystal with
load capacitor CL=18pF. The 22pF frequency fine tuning
capacitors are used C1 and C2. This example also shows general
logic control input handling. For decoupling capacitors, it is
recommended to have one decouple capacitor per power pin.
Each decoupling capacitor should be located as close as
possible to the power pin. The low pass filter R2, C3 and C4
should also be located as close to the VCCA pin as possible.
For LVDS driver, the unused output pairs should be terminated
with a 100Ω resistor across.
VCC
R2
10 C3
10uF
Logic Control Input Examples
Set Logic
VCC _{Input to}
'1'
RU1
1K
To Logic
Input
pins
RD1
Not Install
Set Logic
VCC _{Input to}
'0'
RU2
Not Install
To Logic
Input
pins
RD2
1K
VCCA
C4
0.01u
VCC
C6
0.1u
U1
844004i-04
Zo = 50 Ohm
+
VCCO
R3
100
Zo = 50 Ohm
C7
-
0. 1u
VCC=3.3V
VCCO=3.3V
Zo = 50 Ohm
+
R4
100
X1
C2
19. 44MH z
VCCO
Zo = 50 Ohm
-
33pF
18pF
C8
C9
0. 1u
C1
0.1u
27pF
FIGURE 4. ICS844004I-04 SCHEMATIC EXAMPLE
844004AGI-04
www.icst.com/products/hiperclocks.html
9
REV. A JANUARY 26, 2006