ICS843051 Datasheet, PDF (9/15 Pages) Integrated Circuit Systems – FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS843051
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
LAYOUT GUIDELINE
Figure 3A shows a schematic example of the ICS843051. An
example of LVEPCL termination is shown in this schematic.
Additional LVPECL termination approaches are shown in the
LVPECL Termination Application Note. In this example, an 18 pF
parallel resonant crystal is used.The C1 = 27pF and C2 = 33pF
are recommended for frequency accuracy. The C1 and C2 val-
ues may be slightly adjusted for optimizing frequency accuracy.
VCC
R2
10 C3
10uF
VCCA
C4
0.1u
C2
33pF
XTAL2
19.44MHz
18pF
X1
XTAL1
C1
27pF
VCC
VCC
U1
1
2
3
4
VCCA
VEE
XTAALL_2OUT
XTAALL_1IN
VCC
Q0
8
7
6
nQ0 ₅
FREQ_SEL
ICS843051
R1
1K
Q
VCC
R3
133
Zo = 50 Ohm
Zo = 50 Ohm
nQ
C5
0.1u
R4
82.5
R5
133
+
-
R6
82.5
FIGURE 3A. ICS843051 SCHEMATIC EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 3B shows an example of ICS843051 P.C. board layout.
The crystal X1 footprint shown in this example allows installa-
tion of either surface mount HC49S or through-hole HC49 pack-
age.The footprints of other components in this example are listed
in the Table 6. There should be at least one decoupling capacitor
per power pin. The decoupling capacitors should be located as
close as possible to the power pins. The layout assumes that
the board has clean analog power ground plane.
TABLE 6. FOOTPRINT TABLE
Reference
Size
C1, C2
0402
C3
0805
C4, C5
0603
R2
0603
NOTE: Table 6, lists component
sizes shown in this layout example.
FIGURE 3B. ICS843051 PC BOARD LAYOUT EXAMPLE
843051AG
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9
REV. A DECEMBER 14, 2004