V104 Datasheet, PDF (8/11 Pages) Integrated Circuit Systems – 10 BIT LVDS RECEIVER FOR VIDEO

V104
10 BIT LVDS RECEIVER FOR VIDEO
AC Timing Diagrams
TTL
Outputs
80%
80%
20%
t_TLH
TTL Output
C_L = 8 pF
20%
t_THL
TTL Output Load
PRELIMINARY
TTL Outputs
CLK OUT
2.0 V
t_RCP
Rxn
x = A, B, C, D, E
n = 0, 1, 2, 3, 4, 5, 6
t_RCH
t_RCL
2.0 V 2.0 V
0.8 V 0.8 V
R/F = L
R/F = H
t_RS
t_RH
2.0 V
0.8 V
2.0 V
0.8 V
Phase Lock Loop Set Time
VCC
RCLK+/-
3.0 V
2.0 V
PD
t_RPLL
CLKOUT
2.0 V
V104 Datasheet
8
1/12/05
Revision 1.6
Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel [phone] • www.icst.com