V104 Datasheet, PDF (3/11 Pages) Integrated Circuit Systems – 10 BIT LVDS RECEIVER FOR VIDEO

V104
10 BIT LVDS RECEIVER FOR VIDEO
PRELIMINARY
Pin
Number
6, 7, 8, 10, 11,
12, 13
2
3
4
Pin
Name
RE6 ~ RE0
TEST
PD
OE
5
9, 23, 37, 48
31
1, 16, 30, 44
53
58
64
63
R/F
VCC
CLKOUT
GND
LVCC
LGND
PVCC
PGND
Pin Type
Pin Description
OUT
CMOS/TTL Data Outputs.
IN
IN
IN
IN
Power
OUT
Ground
Power
Ground
Power
Ground
Not used. Tie LOW.
HIGH: normal operation; LOW: Power down (all outputs are “L”).
HIGH: Output enable (normal operation); LOW: Output disable (all outputs
are high impedance).
Output Clock triggering edge select. High: Rising edge; Low: Falling edge.
Power supply pins for TTL outputs and digital circuitry.
Clock out.
Ground pins for TTL outputs and digital circuitry.
Power supply pins for LVDS inputs.
Ground pins for LVDS inputs.
Power supply pin for PLL circuitry.
Ground pin for PLL circuitry.
PD
R/F
OE
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
**Rxn
x = A, B, C, D, E
n = 0, 1, 2, 3, 4, 5, 6
Data Outputs (Rxn)
High impedance
All 0
High impedance
All 0
High impedance
Data Out
High impedance
Data Out
CLKOUT
High impedance
Fixed Low
High impedance
Fixed Low
High impedance
Latches output data on falling edge
High impedance
Latches output data on rising edge
V104 Datasheet
3
1/12/05
Revision 1.6
Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel [phone] • www.icst.com