ICS9250-26 Datasheet, PDF (8/15 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9250-26
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V_DD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Paramete
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unles s otherwis e s tated)
PA RA M ETER
SYM BOL
CONDITIONS
M IN TYP M A X UNITS
Input High Voltage
VIH
2
VDD +0.3
V
Input Low Voltage
VIL
VSS-0.3
0.8
V
Input High Current
IIH
VIN = VD D
-5
5
µA
IIL 1
VIN = 0 V; Inputs with no pull-up res is tors -5
2
Input Low Current
µA
IIL 2
VIN = 0 V; Inputs with pull-up res is tors
-200 -100
I_{DD3 .3 OP}
C_L = 0 pF; Select @ 66 MHz
C_L = 0 pF; Select @ 100 MHz
C_L = 0 pF; Select @ 133 MHz
C_L = Max loads; Select @ 66 MHz
C_L = Max loads; Select @ 100 MHz
97
110
91
105
mA
100 130
275 310
267 300
mA
Operating Supply
C u rre n t
I_{DD2 .5 OP}
C_L = Max loads; Select @ 133 MHz
C_L = 0 pF; Select @ 66 MHz
C_L = 0 pF; Select @ 100 MHz
C_L = 0 pF; Select @ 133 MHz
C_L = Max loads; Select @ 66 MHz
C_L = Max loads; Select @ 100 MHz
278 350
8
10
11
15
mA
13
20
22
70
31
100
mA
Powerdown Current
ID D 3 .3 P D
ID D .2 5 P D
C_L = Max loads; Select @ 133 MHz
C_L = Max loads
Input address VDD or GND
37
130
220 400
µA
<1
10
Input Frequency
Fi
VDD = 3.3 V
12 14.318 16
M Hz
Pin Inductance
Lp i n
7
nH
Input Capacitance¹
CIN
CO U T
Logic Inputs
Output pin capacitance
5
pF
6
pF
Trans ition time¹
Settling time¹
Clk Stabilization¹
CINX X1 & X2 pins
27
Ttrans To 1s t cros s ing of target frequency
Ts
From 1s t cros s ing to 1% target frequency
TSTAB From VDD = 3.3 V to 1% target frequency
45
pF
5
ms
5
ms
5
ms
De la y ¹
tP ZH,tP ZL Output enab le delay (all outputs )
tP HZ,tP LZ Output dis able delay (all outputs )
1
1
10
ns
10
ns
1_{Guaranteed by des ign, not 100% tes ted in production.}
8