ICS9250-26 Datasheet, PDF (6/15 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9250-26
Byte 0: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
Name
Reserved ID
Reserved ID
Reserved ID
Reserved ID
SpreadSpectrum
(1=On/0=Off)
26 48MHz 1
25 48MHz 0
49 CPUCLK2
PWD Description
0 (Active/Inactive)
0 (Active/Inactive)
0 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
0 (Active/Inactive)
Note: Do not write in ID bits, these bits are for ICS internal use only.
Must write a '1' in bit 0 after read back.
Byte 1: Control Register
(1 = enable, 0 = disable)
Bit Pin#
Name
Bit 7 36 SDRAM7
Bit 6 37 SDRAM6
Bit 5 39 SDRAM5
Bit 4 40 SDRAM4
Bit 3 42 SDRAM3
Bit 2 43 SDRAM2
Bit 1 45 SDRAM1
Bit 0 46 SDRAM0
PWD Description
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
Byte 2: Control Register
(1 = enable, 0 = disable)
Bit Pin#
Name
Bit 7 20 PCICLK7
Bit 6 19 PCICLK6
Bit 5 18 PCICLK5
Bit 4 16 PCICLK4
Bit 3 15 PCICLK3
Bit 2 13 PCICLK2
Bit 1 12 PCICLK1
Bit 0 - Reserved
PWD Description
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
1 (Active/Inactive)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
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