ICS9248-96 Datasheet, PDF (8/12 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for Celeron & PII/III™

ICS9248-96
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V_DD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Group Timing Relationship Table
Group
CPU 66MHz
CPU 100MHz
CPU 133MHz
Offset Tolerance Offset Tolerance Offset Tolerance
CPU to SDRAM
2.5ns 500ps 5.0ns 500ps 0.0ns 500ps
CPU to 3V66
7.5ns 500ps 5.0ns 500ps 0.0ns 500ps
SDRAM to 3V66 0.0ns 500ps 0.0ns 500ps 0.0ns 500ps
3V66 to PCI
1.5-3.5ns 500ps 1.5-3.5ns 500ps 1.5-3.5ns 500ps
PCI to PCI
0.0ns 1.0ns 0.0ns 1.0ns 0.0ns 1.0ns
USB & DOT
Async
N/A
Async
N/A
Async
N/A
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A = 0 - 70°C; Supply Voltage V_DD = 3.3 V +/-5%, V_DDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Operating Supply
Current
V_IH
V_IL
I_IH
I_IL1
I_IL2
I_DD3.3OP
I_DD2.5OP
I_DD3.3OP
I_DD2.5OP
I_DD3.3OP
I_DD2.5OP
V_IN = V_DD
V_IN = 0 V; Inputs with no pull-up resistors
V_IN = 0 V; Inputs with pull-up resistors
C_L = Max loads; CPU @ 66 MHz; SDRAM @ 100 MHz
C_L = Max loads; CPU @ 100 MHz; SDRAM @ 100 MHz
C_L = Max loads; CPU @ 133 MHz; SDRAM @ 133 MHz
Power Down Supply
Current
I_DD3.3PD C_L = Max loads; V_IN = V_DD or GND
Input Frequency
F_i
V_DD = 3.3 V
C_IN Logic Inputs
Input Capacitance¹
C_OUT Output pin capacitance
C_INX X1 & X2 pins
Transition time¹
T_trans To 1st crossing of target frequency
Settling time¹
Clk Stabilization¹
T_s From 1st crossing to 1% target frequency
T_STAB From V_DD = 3.3 V to 1% target frequency
1_{Guaranteed by design, not 100% tested in production.}
MIN
2
V_SS - 0.3
-5
-5
-200
TYP
300
12
300
25
300
35
MAX
V_DD + 0.3
0.8
5
UNITS
V
V
mA
mA
340
mA
15
350
mA
30
420
mA
40
300
600
µA
14.31818
5
6
27
45
3
3
3
MHz
pF
pF
pF
ms
ms
ms
0311D—04/23/04
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