ICS91857 Datasheet, PDF (8/14 Pages) Integrated Circuit Systems – Value SSTL_2 Clock Driver (60MHz - 220MHz)

ICS91857
Switching Characteristics for DDRI-400
PARAMETER
SYMBOL
CONDITION
MIN
Low-to high level
propagation delay time
t_PLH1
CLK_IN to any output
High-to low level propagation
delay time
t_PLL1
CLK_IN to any output
Output enable time
t_EN
PD# to any output
Output disable time
t_dis
PD# to any output
Period jitter
T_{jit (per)}
100 - 200 MHz
-50
Half-period jitter
t_{(jit_hper)}
100 - 200 MHz
-75
Input clock slew rate
t_{(sir_I)}
1
Output clock slew rate
t_{(sl_o)}
1
Cycle to Cycle Jitter¹
T_cyc-T_cyc 100 - 200 MHz
-75
Static Phase Offset
t_(spo)3
-50
Output to Output Skew
T_skew
Pulse skew
T_skewp
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. Switching characteristics guaranteed for application frequency range.
3. Static phase offset shifted by design.
TYP
3.5
MAX UNITS
ns
3.5
ns
3
ns
3
ns
50
ps
75
4 V/ns
2 V/ns
75
ps
0
50
ps
75
ps
100 ps
0494C—08/15/05
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