ICS873033 Datasheet, PDF (8/16 Pages) Integrated Circuit Systems – HIGH SPEED, ÷4 DIFFERENTIAL-TO- 3.3V, 5V LVPECL/ECL CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS873033
HIGH SPEED, ÷4 DIFFERENTIAL-TO-
3.3V, 5V LVPECL/ECL CLOCK GENERATOR
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V_CC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V_CC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VCC
Single Ended Clock Input
V_REF
C1
0.1u
R1
1K
PCLK
nPCLK
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 3 shows an example of the differential input that can be
wired to accept single ended levels. The reference voltage level
V generated from the device is connected to the negative
BB
input. The C1 capacitor should be located as close as possible
to the input pin.
VCC
C1
0.1u
CLK_IN
PCLK
VBB
nPCLK
873033AM
FIGURE 3. SINGLE ENDED LVPECL SIGNAL DRIVING
DIFFERENTIAL INPUT
www.icst.com/products/hiperclocks.html
8
REV. A OCTOBER 19, 2005