ICS853111 Datasheet, PDF (8/13 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS853111
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
Z
o
=
50Ω
F_OUT
F_IN
Z_o = 50Ω
50Ω
1
RTT =
Z_o
(V + V / V –2) –2
OH
OL CC
50Ω
RTT
V - 2V
CC
F_OUT
5
2 ^Zo
Z_o = 50Ω
3.3V
5
2 ^Zo
F
IN
Z_o = 50Ω
3
2
Z
o
3
2 ^Zo
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
8 5 3 111 AY
www.icst.com/products/hiperclocks.html
8
REV. D JULY 22, 2003