ICS853111 Datasheet, PDF (2/13 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS853111
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
V_CC
Power
Core supply pin.
Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs.
2
CLK_SEL Input
Pulldown When LOW, selects PCLK0, nPCLK0 inputs.
LVCMOS / LVTTL interface levels.
3
PCLK0 Input
Pulldown Non-inverting differential clock input.
4
nPCLK0
Input
Pullup/Pulldown
Inverting differential LVPECL clock input.
V_CC/2 default when left floating.
5
V_BB
Output
Bias voltage.
6
PCLK1 Input
Pulldown Non-inverting differential clock input.
7
8
9, 16, 25, 32
10, 11
nPCLK1
V_EE
V_CCO
nQ9, Q9
Input
Power
Power
Output
Pullup/Pulldown
Inverting differential LVPECL clock input.
V_CC/2 default when left floating.
Negative supply pin.
Output supply pins.
Differential output pair. LVPECL interface levels.
12, 13
nQ8, Q8 Output
Differential output pair. LVPECL interface levels.
14, 15
nQ7, Q7 Output
Differential output pair. LVPECL interface levels.
17, 18
nQ6, Q6 Output
Differential output pair. LVPECL interface levels.
19, 20
nQ5, Q5 Output
Differential output pair. LVPECL interface levels.
21, 22
nQ4, Q4 Output
Differential output pair. LVPECL interface levels.
23, 24
nQ3, Q3 Output
Differential output pair. LVPECL interface levels.
26, 27
nQ2, Q2 Output
Differential output pair. LVPECL interface levels.
28, 29
nQ1, Q1 Output
Differential output pair. LVPECL interface levels.
30, 31
nQ0, Q0 Output
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
R_PULLDOWN Input Pulldown Resistor
R_VCC/2 Pullup/Pulldown Resistors
Test Conditions
Minimum
Typical
75
50
Maximum
Units
KΩ
KΩ
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
CLKx nCLKx Q0:Q9 nQ0:Q9
Input to Output Mode
Polarity
0
1
LOW HIGH Differential to Differential Non Inverting
1
0
HIGH LOW Differential to Differential Non Inverting
0
Biased;
NOTE 1
LOW
HIGH Single Ended to Differential Non Inverting
1
Biased;
NOTE 1
HIGH
LOW Single Ended to Differential Non Inverting
Biased;
NOTE 1
0
HIGH LOW Single Ended to Differential Inverting
Biased;
NOTE 1
1
LOW HIGH Single Ended to Differential Inverting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to
Accept Single Ended Levels".
8 5 3 111 AY
www.icst.com/products/hiperclocks.html
2
TABLE 3A. CONTROL INPUT
FUNCTION TABLE
Inputs
CLK_SEL Selected Source
0
CLK0, nCLK0
1
CLK1, nCLK1
REV. D JULY 22, 2003