ICS8516I Datasheet, PDF (8/13 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

Integrated
Circuit
Systems, Inc.
ICS8516I
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V_DD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The
ratio of R1 and R2 might need to be adjusted to position the
V_REF in the center of the input voltage swing. For example, if
the input clock swing is only 2.5V and V = 3.3V, V_REF should
DD
be 1.25V and R2/R1 = 0.609.
VDD
Single Ended Clock Input
V_REF
C1
0.1u
R1
1K
CLKx
nCLKx
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 2. In a 100Ω dif-
ferential transmission line environment, LVDS drivers require
a matched load termination of 100Ω across near the receiver
input. For a multiple LVDS outputs buffer, if only partial out-
puts are used, it is recommended to terminate the un-used
outputs.
3.3V
Zo = 50 Ohm
LVDS_Driver
R1
100
Zo = 50 Ohm
3.3V
CLK
nCLK _HiPerClockS
8516FYI
FIGURE 2. TYPICAL LVDS DRIVER TERMINATION
www.icst.com/products/hiperclocks.html
8
REV. A JULY 30, 2004