ICS843081I-01 Datasheet, PDF (8/15 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK MULTIPLIER

Integrated
Circuit
Systems, Inc.
ICS843081I-01
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V, 2.5V LVPECL CLOCK MULTIPLIER
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed
to drive 50Ω transmission lines. Matched impedance tech-
niques should be used to maximize operating frequency and
minimize signal distortion. Figures 3A and 3B show two dif-
ferent layouts which are recommended only as guidelines.
Other suitable clock layouts may exist and it would be rec-
ommended that the board designers simulate to guarantee
compatibility across all printed circuit and clock component
process variations.
Z_o = 50Ω
FOUT
FIN
Z_o = 50Ω
50Ω
RTT =
1
((V_OH + V_OL) / (V_CC – 2)) – 2
Z_o
50Ω
V_CC - 2V
RTT
FOUT
3.3V
125Ω
125Ω
Z_o = 50Ω
FIN
Z_o = 50Ω
84Ω
84Ω
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
843081AGI-01
www.icst.com/products/hiperclocks.html
8
REV. B JANUARY 23, 2006