ICS843-75 Datasheet, PDF (8/12 Pages) Integrated Circuit Systems – 75MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR

Integrated
Circuit
Systems, Inc.
ICS843-75
75MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843-75.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843-75 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V_CC = 3.3V + 0.3V = 3.6V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core) = V
*I
= 3.6V * 110mA = 396mW
MAX
CC_MAX EE_MAX
• Power (outputs)_MAX = 30mW/Loaded Output pair
Total Power_{_MAX} (3.465V, with all outputs switching) = 396mW + 30mW = 426mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockS^TM devices is 125°C.
The equation for Tj is as follows: Tj = θ_JA * Pd_total + T_A
Tj = Junction Temperature
θ_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JA must be used.
Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 6A
below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.426W * 90.5°C/W = 108.6°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air
flow, and the type of board (single layer or multi-layer).
TABLE 6A.THERMAL RESISTANCE θ_JA FOR 8-PIN TSSOP, FORCED CONVECTION
θ_JA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
101.7°C/W
1
90.5°C/W
2.5
89.8°C/W
TABLE 6B. THERMAL RESISTANCE θ_JA FOR 8 LEAD SOIC FORCED CONVECTION
θ_JA by Velocity (Linear Feet per Minute)
0
200
Single-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
128.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
112.7°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
843AG-75
www.icst.com/products/hiperclocks.html
REV. A JANUARY 9, 2006
8