ICS843-75 Datasheet, PDF (7/12 Pages) Integrated Circuit Systems – 75MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR

Integrated
Circuit
Systems, Inc.
ICS843-75
75MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
FREQUENCY STABILITY
The table shown below provides a basic guideline in se-
lecting the proper quartz crystal that meets a timing budget
of ±100ppm. For more information on selecting the proper
crystal, see the application note, Crystal Timing Budget
and Accuracy for FemtoClock™ .
Parameter
Frequency Tolerance
Frequency Stability
Aging for 10 Years
Accuracy of ICS Oscillator
Load Capacitance Accuracy
Total Overall Timing Error
Typical
±30
±30
±15
±10
±3
±88
Units
ppm
ppm
ppm
ppm
ppm
ppm
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs.Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50Ω transmission lines.Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 2A and 2B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
Z_o = 50Ω
FOUT
FIN
Z_o = 50Ω
50Ω
RTT =
1
((V_OH + V_OL) / (V_CC – 2)) – 2
Z_o
50Ω
V_CC - 2V
RTT
FIGURE 2A. LVPECL OUTPUT TERMINATION
FOUT
3.3V
125Ω
125Ω
Z_o = 50Ω
FIN
Z_o = 50Ω
84Ω
84Ω
FIGURE 2B. LVPECL OUTPUT TERMINATION
843AG-75
www.icst.com/products/hiperclocks.html
7
REV. A JANUARY 9, 2006