ICS84021 Datasheet, PDF (8/14 Pages) Integrated Circuit Systems – 260MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
ICS84021
260MHZ, CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER
TABLE 7A. AC CHARACTERISTICS, V_DD = V_DDA = V_DDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
F_OUT
Output Frequency
N÷3
103.3
7.5
260
MHz
10
ps
tjit(per) Period Jitter, RMS; NOTE 1
N÷4
N÷5
4.3
7
ps
4.1
6
ps
N÷6
12.9
16
ps
tsk(o) Output Skew; NOTE 2, 3
100
ps
t_R / t_F
Output Rise/Fall Time
M, N to nP_LOAD
20% to 80%
300
5
800
ps
ns
t_S
Setup Time S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
ns
5
ns
M, N to nP_LOAD
5
ns
t_H
Hold Time S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
ns
5
ns
odc
Output Duty Cycle
45
55
%
t_LOCK
PLL Lock Time
1
ms
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE
7B.
AC
CHARACTERISTICS,
V
DD
=
V
DDA
=
3.3V±5%,
V
DDO
=
2.5V±5%,
TA
=
0°C
TO
70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
F_OUT
Output Frequency
N÷3
103.3
6.4
260
MHz
8
ps
tjit(per) Period Jitter, RMS; NOTE 1
N÷4
N÷5
4.3
8
ps
4.2
7
ps
N÷6
9
12
ps
tsk(o) Output Skew; NOTE 2, 3
90
ps
t_R / t_F
Output Rise/Fall Time
M, N to nP_LOAD
20% to 80%
300
5
800
ps
ns
t_S
Setup Time S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
ns
5
ns
M, N to nP_LOAD
5
ns
t_H
Hold Time S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
ns
5
ns
odc
Output Duty Cycle
45
55
%
t_LOCK
PLL Lock Time
1
ms
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
84021AY
www.icst.com/products/hiperclocks.html
8
REV. A NOVEMBER 7, 2003