ICS84021 Datasheet, PDF (3/14 Pages) Integrated Circuit Systems – 260MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
ICS84021
260MHZ, CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
2, 3, 4,
28, 29,
30, 31, 32
5, 6
M5
M6, M7, M8,
M0, M1,
M2, M3, M4
N0, N1
Input
Input
Pullup
M divider inputs. Data latched on LOW-to-HIGH transition
Pulldown ^{of nP_LOAD input. LVCMOS / LVTTL interface levels.}
Input
Pulldown
Determines output divider value as defined in Table 3C,
Function Table. LVCMOS / LVTTL interface levels.
7
nc
Unused
No connect.
8, 16
GND
Power
Power supply ground.
9
TEST
Output
Test output which is ACTIVE in the serial mode of operation. Output
driven LOW in parallel mode. LVCMOS / LVTTL interface levels.
10
11, 12
V_DD
OE1, OE0
Power
Input
Pullup
Core supply pin.
Output enable. When logic HIGH, the outputs are enabled (default).
When logic LOW, the outputs are in Tri-State. See Table 3E,
OE Function Table. LVCMOS / LVTTL interface levels.
13
14, 15
V_DDO
Q0, Q1
Power
Output
Output supply pin.
Clock outputs. LVCMOS / LVTTL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the outputs to go low. When logic LOW, the
17
MR
Input Pulldown internal dividers and the outputs are enabled. Assertion of MR
does not effect loaded M, N, and T values.
LVCMOS / LVTTL interface levels.
18
S_CLOCK
Input
Pulldown
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
19
S_DATA
Input
Pulldown
Shift register serial input. Data sampled on the rising edge of
S_CLOCK. LVCMOS / LVTTL interface levels.
20
S_LOAD
Input
Pulldown
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
21
V_DDA
Power
Analog supply pin.
Selects between crystal or test inputs as the PLL reference source.
22
XTAL_SEL
Input Pullup Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW.
LVCMOS / LVTTL interface levels
23
TEST_CLK
Input Pulldown Test clock input. LVCMOS / LVTTL interface levels.
24, 25
XTAL2, XTAL1
Input
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
Parallel load input. Determines when data present at M8:M0 is
26
nP_LOAD
Input Pulldown loaded into M divider, and when data present at N1:N0 sets the
N output divider value. LVCMOS / LVTTL interface levels.
27
VCO_SEL
Input
Pullup
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
84021AY
www.icst.com/products/hiperclocks.html
3
REV. A NOVEMBER 7, 2003