ICS840021I Datasheet, PDF (8/11 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
ICS840021I
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
APPLICATION SCHEMATIC
Figure 3A shows a schematic example of the ICS840021I. An
example of LVCMOS termination is shown in this schematic.
Additional LVCMOS termination approaches are shown in the
LVCMOS Termination Application Note. In this example, an 18pF
parallel resonant 25MHz crystal is used for generating 125MHz
output frequency. The C1 = 22pF and C2 = 33pF are recom-
mended for frequency accuracy. For different board layout, the
C1 and C2 values may be slightly adjusted for optimizing fre-
quency accuracy.
VD D
VD D A
R2 C3
10
10uF
C4
0.1u
OE
C2
X1
33pF
U1
1
2
VDDA
3 ^OE
4 ^XTAL_OUT
XTAL_I N
I C S840021i
C1
22pF
VD D =3 .3 V
VD D
8
7
Q0 ₆
GND ₅
NC
R3
VD D
33
Q
C5
0.1u
Zo = 50 Ohm
LVCMOS
FIGURE 3A. ICS840021I SCHEMATIC EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 3B shows an example of ICS840021I P.C. board layout.
The crystal X1 footprint shown in this example allows installa-
tion of either surface mount HC49S or through-hole HC49 pack-
age. The footprints of other components in this example are listed
in the Table 7. There should be at least one decoupling capacitor
per power pin. The decoupling capacitors should be located as
close as possible to the power pins. The layout assumes that
the board has clean analog power ground plane.
TABLE 7. FOOTPRINT TABLE
Reference
Size
C1, C2
0402
C3
0805
C4, C5
0603
R2, R3
0603
NOTE: Table 7, lists component
sizes shown in this layout example.
FIGURE 3B. ICS840021I PC BOARD LAYOUT EXAMPLE
840021AGI
www.icst.com/products/hiperclocks.html
8
REV. A MAY 19, 2005