ICS950805 Datasheet, PDF (7/20 Pages) Integrated Circuit Systems – Frequency Generator with 200MHz Differential CPU Clocks

ICS950805
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V_DD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +85°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A = 0 - 70C; Supply Voltage V_DD = 3.3 V +/-5%
PARAMETER SYMBOL
CONDITIONS
MIN
TYP
Input High Voltage
V_IH
2
Input Low Voltage
V_IL
V_SS-0.3
Input High Current
I_IH
V_IN = V_DD
-5
I_IL1 V_IN = 0 V; Inputs with no pull-up resistors
-5
Input Low Current
MAX
V_DD+0.3
0.8
5
UNITS
V
V
mA
mA
Operating Supply
Current
I_IL2
I_DD3.3OP
V_IN = 0 V; Inputs with pull-up resistors
C_L = Full load; Select @ 100 MHz
-200
229
230
360
mA
I_{DD3.3OP CL =Full load; Select @ 133 MHz}
220
233
360
mA
Powerdown Current I_DD3.3PD IREF=5 mA
38.1
45
mA
Input Frequency
F_i
V_DD = 3.3 V
14.318
MHz
Pin Inductance
L_pin
7
nH
Input Capacitance¹
C_IN
C_OUT
Logic Inputs
Output pin capacitance
5
pF
6
pF
C_INX X1 & X2 pins
27
36
45
pF
Transition time¹
Settling time¹
T_trans
T_s
To 1st crossing of target frequency
From 1st crossing to 1% target frequency
3
ms
3
ms
Clk Stabilization¹
T_STAB From V_DD = 3.3 V to 1% target frequency
1
3
ms
Time to first clock¹
T_1C Time to first clock
1.8
ms
Delay¹
t_PZH,t_PZL Output enable delay (all outputs)
t_PHZ,t_PLZ Output disable delay (all outputs)
1
1
10
ns
10
ns
1_{Guaranteed by design, not 100% tested in production.}
0649H—02/25/05
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