ICS950805 Datasheet, PDF (5/20 Pages) Integrated Circuit Systems – Frequency Generator with 200MHz Differential CPU Clocks

ICS950805
Byte 2: Control Register
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin#
10
11
12
13
16
17
18
-
Name
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
-
PWD
1
1
1
1
1
1
1
0
Type
RW
RW
RW
RW
RW
RW
RW
-
Description
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
(Reserved)
Byte 3: Control Register
Bit
Bit 0
Bit 1
Bit 2
Pin#
5
6
7
Name
PCICLK_F0
PCICLK_F1
PCICLK_F2
Bit 3 5 PCICLK_F0
Bit 4 6 PCICLK_F1
Bit 5
Bit 6
Bit 7
7 PCICLK_F2
39 48MHz_USB
38 48MHz_DOT
PWD
1
1
1
0
0
0
1
1
Type
RW
RW
RW
RW
RW
RW
RW
RW
Description
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
Allow control of PCICLK_F0 with assertion of
PCI_STOP#. 0=Free Running, 1=Not free
running
Allow control of PCICLK_F1 with assertion of
PCI_STOP#. 0=Free Running, 1=Not free
running
Allow control of PCICLK_F2 with assertion of
PCI_STOP#. 0=Free Running, 1=Not free
running
0=Disabled 1=Enabled
0=Disabled 1=Enabled
Byte 4: Control Register
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin#
21
22
23
24
35
33
-
-
Name
66MHz_OUT0/3V66-2
66MHz_OUT0/3V66-3
66MHz_OUT0/3V66-4
3V66_5
3V66_1/VCH_CLK
3V66_0
-
-
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
PWD
1
1
1
1
1
1
0
0
Type
RW
RW
RW
RW
RW
RW
R
R
Description
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
(Reserved)
(Reserved)
0649H—02/25/05
5